1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a coded mask read only memory (ROM) and a method for coding a mask ROM.
2. Discussion of the Related Art
A conventional method for coding a mask read-only memory (ROM) will be explained with reference to the accompanying drawings.
FIGS. 1a through 1d are cross-sectional views showing process steps of a method for coding a mask ROM. Referring to FIG. 1a, field regions and active regions are defined on a first conductive type semiconductor substrate 1. Next, field ion implantation into the field regions of the substrate 1 is performed to form a plurality of field oxide layers 2 which are separated from one another by a predetermined distance. Then, from one another by a predetermined distance. Then, implantation of depletion ions into the entire surface of the semiconductor substrate 1 inclusive of the field oxide layers 2 is performed. In this case, since a channel should be of an N-type in an NMOS depletion mode, arsenic ions, which are impurity ions of the N-type, are used as the depletion ions.
Referring to FIG. 1b, a polycrystalline silicon layer is formed on the entire surface of the semiconductor substrate 1 inclusive of the field oxide layer 2, and subjected to a photolithography process to pattern the polycrystalline silicon into gate electrodes 3 on the active regions of the semiconductor substrate 1. Subsequently, an oxide layer is formed over the entire surface of the semiconductor substrate 1 inclusive of the gate electrodes 3, and subjected to etch-back to form gate sidewalls 4 on both sides of each of the gate electrodes 3.
Referring to FIG. 1c, with the gate electrodes 3 and the sidewalls 4 serving as masks, a source and drain ion implantation process is performed to respectively form source and drain impurity regions 5 and 6 in the semiconductor substrate 1 at the sides of each of the gate electrodes 3. Subsequently, in order to form an off-transistor, according to a customer's demands, using code ion implantation, all regions except a selected one of the gate electrodes 3 are masked. That is, a photoresist layer 7 is coated over the entire surface of the semiconductor substrate 1 inclusive of the selected gate electrode 3. Then the photoresist layer 7 is patterned to expose only the selected gate electrode 3. Next, with the photoresist pattern 7 serving as a mask, code ions are implanted through the selected gate electrode 3 to form the off-transistor.
Referring to FIG. 1d, the remaining photoresist 7 is removed to complete the formation of the on-transistors and the off-transistor. As a result, data-coding is completed.
FIG. 2a is a graph showing operation characteristics of a conventional depletion type transistor, and FIG. 2b is a graph showing operation characteristics of a conventional enhancement type transistor.
As shown by FIGS. 2a and 2b, a channel is formed in a depletion type transistor even though a positive voltage is not applied to a gate electrode, and a channel is formed in an enhancement type transistor as long as a voltage higher than a threshold voltage is applied to the gate electrode.
The conventional method for coding a mask ROM has disadvantages. Since code ion implantation is carried out in the channel region, the substrate in the channel region is damaged. Moreover, the substrate damage increases the resistance to current flowing along the channel region; thus disturbing the current flow.